1. Field of the Invention
The embodiments described herein are directed to methods for fabricating non-volatile memory devices, and more particularly to methods for fabricating floating-gate memory devices using virtual ground arrays.
2. Background of the Invention
FIG. 1 is a schematic representation of a conventional floating gate memory cell 100. Memory cell 100 comprises a substrate 102 with diffusion regions 104 and 106 formed therein. The diffusion regions correspond to the source and drain of FET-type device. According to one example, substrate 102 can be a P-type substrate and diffusion regions 104 and 106 can be N-type diffusion regions. In other embodiments, cell 100 can comprise an N-type substrate 102 with P-type diffusion regions 104 and 106. Although it will be understood that a P-type substrate is generally preferred.
Cell 100 further comprises a gate dielectric layer, sometimes referred to as a tunnel dielectric layer 108 formed over substrate 102 between diffusion regions 104 and 106. A floating gate 110 is then formed over gate dielectric 108. Floating gate 110 is typically formed from a polysilicon. An inter—polysilicon (poly) dielectric layer 112 then separates floating gate 110 from a control gate 114. Control gate 114 is also typically formed from polysilicon. Inter-poly dielectric layer 112 can be formed from, e.g., a silicon dioxide (SiO2) material. In other embodiments, inter-poly dielectric 110 can comprise a multi-layer structure such as an Oxide-Nitride-Oxide (ONO) structure.
In operation, a high voltage is applied to control gate 114 in order to program cell 100. This voltage is coupled with floating gate 110 via a control gate capacitance (CCG). The coupled voltage causes an inversion channel to be formed in the upper layer of substrate 102 between diffusion regions 104 and 106. Voltages are then applied to diffusion regions 104 and 106 so as to create a large lateral electric field that will cause carriers to flow through the channel, e.g., from one diffusion region towards the other.
The voltage coupled with floating gate 110 will create an electric field sufficient to cause some of the carriers to tunnel through gate dielectric 108 into floating gate 110. In other words, the voltage coupled with floating gate 110 needs to be capable of producing an electric field that can supply the carriers with enough energy to allow them to overcome the barrier height of gate dielectric 108. Accordingly, as mentioned above, sufficient coupling between control gate 114 and floating gate 110 is required in order to ensure that an adequate field is present to induce carriers to pass through gate dielectric 108 onto floating gate 110.
It is well known to use virtual ground array designs in order to reduce the cell size for floating gate memory cells and non-volatile memory products, such as flash memory products. Smaller cell sizes, however, often require smaller buried diffusion sizes, which are not necessarily compatible with conventional processing techniques.
For example, one problem that can occur as a result of the reduced buried diffusion sizes with conventional fabrication techniques is a reduced gate coupling ratio (GCR) between the control gate and floating gate. Sufficient coupling is needed in order to ensure that an adequate field is present in the memory cell to induce carriers to pass through the tunnel oxide layer into the floating gate.
As is understood, the GCR is a function of the CGC as well as the Source Capacitance (CS), Bulk Capacitance (CB), and Drain Capacitance (CD) illustrated in FIG. 1. The relationship is defined as:GCR=CCG/(CS+CB+CD+CCG)
Accordingly, the GCR can be increased by increasing CCG, or by decreasing the Source Capacitance (CS) or Drain Capacitance (CD). Thus, by increasing the distance between floating gate 110 and buried diffusion regions 104 and 106, source and drain capacitances (CS, CD) can be decreased. As a result, the gate coupling ratio (GCR) of the memory device can be improved. Accordingly, it is important to maintain adequate GCR in virtual ground arrays, despite the smaller buried diffusion sizes.